Publication

Google Scholar Webpage

• H. Liu, P. Schuddinck, Y. Xiang, Z. Pei, L. Verschueren, H. Mertens, S. Salahuddin, G. Hiblot, B. Chan, S. Subramanian, P. Weckx, G. Hellings, M. Garcia Bardon, J. Ryckaert, C. Pan, and F. Catthoor, “CFET SRAM with Double-sided Interconnect Design and DTCO Benchmark”, in IEEE Transactions on Electron Devices (TED), October 2023.
• C. Mao, Z. Mu, Z. Chen, Q. Liang, I. Schizas, and C. Pan, “Deep Learning in Physical Layer Communications: Evolution and Prospects in 5G and 6G Networks”, in IET Communications, August 2023.
• L. Shang, S. Lu, S. Jung, and C. Pan, “Novel Fence Generation Methods for Accelerating Reconfigurable Exact Synthesis”, IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS), Phoenix, AZ, August 2023.
• S. Lu, L. Shang, S. Jung, and C. Pan, “A Technology/Circuit Co-design Framework for Emerging Reconfigurable Devices”, IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS), Phoenix, AZ, August 2023.
• Z. Pei, M. Mayahinia, H. H. Liu, M. Tahoori, S. M. Salahuddin, F. Catthoor, Z. Tokei, and C. Pan, “Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect”, Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), Knoxville, TN, June 2023.
• C. Mao, Q. Liang, and C. Pan, “A Statistical Approach for Neural Network Pruning with Application to Internet of Things”, in Journal on Wireless Communications and Networking, June 2023.
• Z. Pei, M. Mayahinia, H. H. Liu, M. Tahoori, S. M. Salahuddin, F. Catthoor, Z. Tokei, and C. Pan, “Emerging Interconnect Exploration for SRAM Application Using Non-Conventional H-Tree and Center-Pin Access”, 24^th IEEE International Symposium on Quality Electronic Design (ISQED), San Francisco, CA, April 2023.
• L. Shang, A. Naeemi, and C. Pan, “Towards Area Efficient Logic Circuit: Exploring The Potential of Reconfigurable Gate by DAG-Aware Synthesis”, in IEEE Open Journal of the Computer Society (OJCS), March 2023.
• Z. Pei, M. Mayahinia, H. H. Liu, M. Tahoori, F. Catthoor, Z. Tokei, and C. Pan, “Graphene-based Interconnect Exploration for Large SRAM Caches for Ultra-Scaled Technology Nodes”, in IEEE Transactions on Electron Devices (TED), vol. 70, no. 1, pp. 230-238, January 2023.
• H. Park, S. Laskhminarayana, L. H. T. Nguyen, C. Pan, and S. Jung, “Portable Indoor Air Quality Measurement System”, IEEE International Conference on e-Health and Bioengineering (EHB), Iasi, Romania, November 2022.
• D. Bhole, Q. Liang, and C. Pan, “Neural Network for UWB Radar Sensor Network-Based Sense-Through-Wall Human Detection”, 11th International Conference on Communications, Signal Processing, and Systems (CSPS), Changbaishan, China, October 2022.
• L. Shang, S. Jung, and C. Pan “Fault-Aware Adversary Attack Analyses and Enhancement for RRAM-based Neuromorphic Accelerator”, in Frontiers in Sensors, May 2022.
• H. Park, S. Lakshminarayana, C. Pan, H. Chung, and S. Jung, “An Auto Adjustable Transimpedance Readout System for Wearable”, in Electronics, 11 no. 8, April 2022.
• Z. Pei, A. Dutta, L. Shang, S. Jung, and C. Pan, “Interconnect Technology/System Co-Optimization for Low-Power VLSI Applications Using Ballistic Materials,” IEEE Transactions on Electron Devices (TED), May 2021.
• Pei, L. Shang, S. Jung, and C. Pan, “Deep Pipeline Circuit for Low-Power Spintronic Devices,” IEEE Transactions on Electron Devices (TED), April 2021.
• L. Shang, M. Adil, R. Madani, and C. Pan, “Fast Linear Programming Optimization Using Crossbar-Based Analog Accelerator,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Limassol, Cyprus, July 2020.
• L. Shang, M. Adil, R. Madani, and C. Pan, “Memristor-Based Analog Recursive Computation Circuit for Linear Programming Optimization,” in IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), May 2020.
• Y. Liao, C. Pan, and A. Naeemi, “Benchmarking and Optimization of Spintronic Memory Arrays,” in IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), May 2020.
• R. Nashed, C. Pan, X. Wu, F. Catthoor, Z. Tokei, and A. Naeemi, “Accurate Determination of Interlayer Resistivity of Two-Dimensional Layered Systems: Graphene Case study,” IEEE Transactions on Electron Devices (TED), February 2020.
• C. Pan, Q. Lou, M, Niemier, X. S. Hu, and A. Naeemi, “Energy-Efficient Convolutional Neural Network based on Cellular Neural Network Using Beyond-CMOS Technologies,” IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), December 2019.
• Q. Lou, C. Pan, J, Mcguinness, A. Horvath, A. Naeemi, M, Niemier, X. S. Hu, “A mixed-signal architecture for convolutional neural networks”, ACM Journal on Emerging Technologies in Computing Systems (JETC), April 2019.
• C. Pan, S. Dutta, and A. Naeemi, “Magnetoelectric Computational Devices,” Patent No. US 10,177,769 B2, Jan. 8, 2019.
• C. Pan and A. Naeemi, “Complementary Logic Implementation for Antiferromagnet Field-Effect Transistors,” IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), December 2018.
• R. Nashed, C. Pan, K. Brenner, and A. Naeemi, “Field Emission from Graphene Sheets and its Application in Floating Gate Memories,” Semiconductor Science and Technology, October 2018.
• C. Pan and A. Naeemi, “Energy-Efficient Antiferromagnet Field-Effect Transistor Logic Implementation”, US Provisional Patent App. 62/719,280, Aug. 17, 2018.
• C. Pan and A. Naeemi, “Transient Performance Analysis and Optimization of Crossbar Memory Arrays Using NbO2-based Threshold Switching Selectors,” IEEE Transactions on Electron Devices, July 2018.
• C. Hsu, C. Pan, and A. Naeemi, “Performance Analysis and Enhancement of Negative Capacitance Logic Devices Based on Internally Resistive Ferroelectrics,” IEEE Electron Device Letters (EDL), April 2018. (Editor’s Pick)
• V. Huang, C. Pan, and A. Naeemi, “Generic System-Level Modeling and Optimization for Beyond CMOS Device Applications,” IEEE International Symposium on Quality Electronic Design (ISQED), March 2018.
• C. Pan and A. Naeemi, “An Expanded Benchmarking of Beyond-CMOS Devices Based on Boolean and Neuromorphic Representative Circuits,” IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), January, 2018.
• C. Pan and A. Naeemi, “A Non-volatile Fast Read Two-transistor SRAM based on Spintronic Devices,” IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), November 2017.
• C. Pan and A. Naeemi, “Beyond-CMOS Non-Boolean Logic Benchmarking: Insights and Future Directions,” Design Automation and Test in Europe (DATE), March 2017.
• C. Pan and A. Naeemi, “Non-Volatile Spintronic Memory Array Performance Benchmarking based on Three-Terminal Memory Cell,” IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), February 2017.
• C. Pan and A. Naeemi, “Non-Boolean Computing Benchmarking for beyond-CMOS Devices based on Cellular Neural Network,” IEEE Journal of Exploratory Solid-State Computational Devices and Circuits (JxCDC), December 2016.
• D. Prasad, C. Pan, and A. Naeemi, “Modeling Interconnect Variability at Advanced Technology Nodes and Potential Solutions,” IEEE Transactions on Electron Devices (TED), December 2016.
• J. Mohseni, C. Pan, and A. Naeemi, “Performance Modeling and Optimization for On-Chip Interconnects in Cross-Bar ReRAM Memory Arrays,” IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), October, 2016.
• D. Prasad, C. Pan, and A. Naeemi, “Interconnect design and optimization for advanced technology nodes,” Proceedings of SRC TECHCON, September 2016. (Best in Session Award)
• S. Dutta, R. M. Iraei, C. Pan, D. Nikonov, S. Manipatruni, I. A. Young, and A. Naeemi, “Impact of Spintronics Transducers on the Performance of Spin Wave Logic Circuit,” IEEE International Conference on Nanotechnology (NANO), August 2016.
• C. Pan and A. Naeemi, “A Proposal for Energy-Efficient Cellular Neural Network Based on Spintronic Devices,” IEEE Transactions on Nanotechnology (TNANO), August 2016.
• R. Nashed, C. Pan, K. Brenner, and A. Naeemi, “Ultra-High Mobility in Dielectrically Pinned CVD Graphene,” IEEE Journal of the Electron Devices Society (JEDS), July 2016.
• C. Pan and A. Naeemi, “Beyond-CMOS Device and Interconnect Technology Benchmarking based on a Fast Cross-Layer Optimization Methodology,” Electrochemical Society (ECS) Transaction, May 2016. (Invited Paper)
• C. Pan, S. Chang, and A. Naeemi, “Performance Analyses and Benchmarking for Spintronic Devices and Interconnects,” IEEE International Interconnect Technology Conference (IITC), May 2016.
• J. Mohseni, C. Pan, and A. Naeemi, “Performance Modeling and Optimization for On-Chip Interconnects in STT-MRAM Memory Arrays,” IEEE International Interconnect Technology Conference (IITC), May 2016. (Top 5 Student Papers)
• C. Pan and A. Naeemi, “Interconnect Design and Benchmarking for Charge-based Beyond-CMOS Device Proposals,” IEEE Electron Device Letters (EDL), April 2016.
• D. Prasad, C. Pan, and A. Naeemi, “Impact of Interconnect Variability on Circuit Performance in Advanced Technology Nodes,” IEEE International Symposium on Quality Electronic Design (ISQED), March 2016. (Best Paper Nomination)
• J. Mohseni, C. Pan, and A. Naeemi, “Performance Modeling and Optimization for On-Chip Interconnects in 2D and 3D Memory Arrays,” IEEE International Symposium on Quality Electronic Design (ISQED), March 2016.
• V. Huang, C. Pan, and A. Naeemi, “Device/System Performance Modeling of Stacked Lateral NWFET Logic,” IEEE International Symposium on Quality Electronic Design (ISQED), March 2016.
• D. Prasad, A. Ceyhan, C. Pan, and A. Naeemi, “Adapting Interconnect Technology to Multi-Gate Transistors for Optimum Performance,” IEEE Transactions on Electron Devices (TED), December 2015.
• C. Pan, P. Raghavan, D. Yakimets, P. Debacker, F. Catthoor, N. Collaert, Z. Tokei, D. Verkest, A. Thean, and A. Naeemi, “Technology/System Co-Design and Benchmarking for Lateral and Vertical GAA Nanowire FETs at 5nm Technology Node,” IEEE Transactions on Electron Devices (TED), October 2015.
• J. Mohseni, C. Pan, and A. Naeemi, “Performace Modeling and Optimization for On-Chip Interconnects in Memory Arrays,” IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), October 2015.
• C. Pan, R. Baert, I. Ciofi, Z. Tokei, and A. Naeemi, “System-level Variation Analysis for Interconnection Networks at Sub-10nm Technology Nodes Using Multiple Patterning Techniques,” IEEE Transactions on Electron Devices (TED), July 2015.
• C. Pan, P. Raghavan, A. Ceyhan, F. Catthoor, Z. Tokei, and A. Naeemi, “Technology/Circuit/System Co-Optimization and Benchmarking for Multilayer Graphene Interconnects at Sub-10nm Technology Node,” IEEE Transactions on Electron Devices (TED), May 2015.
• C. Pan, P. Raghavan, F. Catthoor, Z. Tokei, and A. Naeemi, “Technology/Circuit Co-Optimization and Benchmarking for Multilayer Graphene Interconnects at Sub-10nm Technology Node,” IEEE International Symposium on Quality Electronic Design (ISQED), March 2015. (Best Paper Nomination)
• C. Pan and A. Naeemi, “A Paradigm Shift in Local Interconnect Technology Design in the Era of Nanoscale Multi-Gate and Gate-All-Around Devices,” IEEE Electron Device Letters (EDL), March 2015.
• C. Pan and A. Naeemi, “A Fast System-Level Design Methodology for Heterogeneous Multi-core Processors Using Emerging Technologies,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), March 2015.
• C. Pan and A. Naeemi, “System-Level Chip/Package Co-Design for Multi-Core Processors Implemented with Power-Gating Technique,” IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), October 2014.
• Naeemi, A. Ceyhan, V. Kumar, C. Pan, R. M. Iraei, and S. Rakheja, “BEOL Scaling Limits and Next Generation Technology Prospects,” IEEE/ACM Design Automation Conference (DAC), June 2014. (Invited Paper)
• C. Pan and A. Naeemi, “System-level Variation Analysis for Interconnection Networks,” IEEE International Interconnect Technology Conference (IITC), May 2014.
• C. Pan, S. Mukhopadhyay, and A. Naeemi, “An Analytical Approach to System-level Variation Analysis and Optimization for Multi-Core Processors,” IEEE International Symposium on Quality Electronic Design (ISQED), March 2014.
• C. Pan and A. Naeemi, “A Proposal for a Novel Aluminum-Copper Hybrid Interconnect Technology for the End of Roadmap,” IEEE Electron Device Letters (EDL), February 2014.
• C. Pan and A. Naeemi, “System-level Analysis for 3D Interconnection Networks,” IEEE International Interconnect Technology Conference (IITC), June 2013.
• C. Pan, A. Ceyhan, and A. Naeemi, “System-level Optimization and Benchmarking for InAs Nanowire Based Gate-All-Around Tunneling FETs,” IEEE International Symposium on Quality Electronic Design (ISQED), March 2013.
• C. Pan and A. Naeemi, “System-Level Performance Optimization and Benchmarking for On-Chip Graphene Interconnects,” IEEE Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), October 2012.
• C. Pan and A. Naeemi, “System-Level Optimization and Benchmarking of Graphene pn Junction Logic System Based on Empirical CPI Model,” IEEE International Conference on IC Design and Technology (ICICDT), May 2012. (Best Paper Award)
• C. Pan and A. Naeemi, “Device- and System-Level Performance Modeling for Graphene P-N Junction Logic,” IEEE International Symposium on Quality Electronic Design (ISQED), March 2012. (Best Paper Award)