1. Energy-Efficient Reconfigurable Computing Circuits and Systems
As traditional CMOS technology scaling nears its physical limits, reconfigurable computing circuits offer a promising alternative to enhance energy and area efficiency. These circuits are made of logic devices that can transform input-output mapping in real-time, enabling high computation density and low cost for a range of applications. This project aims to use a synergistic device-circuit-synthesis co-optimization approach to develop novel synthesis solutions and leverage emerging reconfigurable logic devices. A simple block-level circuit demonstration is shown below, where Figure (c) shows the proposed reconfigurable circuit that only consumes four nodes, where the same circuit performs either function depending on the control signal, reducing the logic cell usage by 1/3 without the need for MUXs.
2. Neuromorphic Computing Circuit Using Emerging Technologies
Biologically-inspired computing platforms are highly-efficient for solving many problems, particularly in the voice, image, and video processing, by taking advantages of massive parallel low-power computing blocks. Compounded with emerging beyond-CMOS technologies, these neuromorphic circuits lead to significant improvement in computing energy efficiency. As an example, cellular neural network (CNN) is one promising type of non-Boolean computing system that can outperform the traditional digital logic computation and mitigate the physical scaling limit of the conventional CMOS technology.
3. Emerging Non-Volatile Memory Design
To replace the conventional SRAM, DRAM, and floating gate-based FLASH memory, this project aims to develop high-density high-performance stand-alone non-volatile memory that is essential for energy-efficient computing systems. A variety of emerging technologies and memory architectures are investigated, and two examples are given as follow.
- Spintronic Memory
- 3D Crossbar Memory Array
4. Hierarchical Optimization for Generic VLSI Systems
To design next-generation high-performance low-power VLSI computing systems, this project develops a fast and efficient hierarchical optimization engine to explore various emerging beyond-CMOS technologies and system-level innovations. When developing new technology options, all critical design parameters across all levels of abstraction must be co-optimized simultaneously to maximize the overall chip throughput. A faster device does not guarantee a larger chip throughput, because the system could be limited by the leakage power, device footprint area, interconnect network, architecture, and/or memory bandwidth. The proposed optimization engine is highly efficient so that an exhaustive exploration and searching is feasible under area or power constraints. Several representative case studies are listed as follow:
| Device Optimization: | Interconnect Optimization: | System-Level Optimization: |
4. Beyond-CMOS Technology Exploration for Boolean and non-Boolean Applications
Faced with the challenges and limitations of CMOS scaling, there is a global search for beyond-CMOS device technologies that are capable of augmenting or even replacing conventional Si CMOS technology and sustaining Moore’s Law. There is an increasing need for a uniform benchmarking methodology to capture and evaluate the latest research and development for various beyond-CMOS proposals. Such research is critical in identifying the key limiting factors for promising devices and in guiding future research directions through modification or even reinvention of proposed devices.
Acknowledgement
We acknowledge the support from our collaborators and sponsors, including Department of Energy (DOE), National Science Foundation (NSF), and imec.
