Born into an ordinary family, Dr. Pei developed resilience early in life. Prior to university, he combined rigorous academic preparation with a significant personal transformation through long-distance running, cultivating discipline and endurance, qualities that later underpinned his academic and industrial achievements.

He holds an M.S. in Electrical Engineering from Columbia University, a Ph.D. in Electrical Engineering from the University of Texas at Arlington, and works as a postdoctoral fellow in the Department of Electrical and Computer Engineering at the University of Alabama. His research spans IC/VLSI design, bridging technology nodes and top-level software applications, with a focus on AI integration.

During his doctoral studies, he collaborated with IMEC on the Cacti++ EDA/CAD tool, addressing gaps in early-stage cache system co-design and co-optimization, and supporting verification of SRAM cache PPA across hardware and software parameters. In industry, he worked as a senior design engineer at Cadence, gaining expertise in the full RTL-to-GDSII workflow for tapeout.