Connect VDD/GND to Pins

OR gate requires VDD connected to one input D3 of majority gate.

AND gate requires GND connected to one input D3 of majority gate.

MAJx2_DFFLQNx4_OR2x2_ASAP7_75t_L reg2 ( .D1( n1 ), .D2( n15 ), .Y( n2 ), .CLK( clk ) );

MAJx2_DFFLQNx4_AND2x2_ASAP7_75t_L reg4 ( .D1( n3 ), .D2( n5 ), .Y( n16 ), .CLK( clk ) );

How to connect VDD to D3 of MAJx2_DFFLQNx4_OR2x2_ASAP7_75t_L? or how to connect GND to D3 of MAJx2_DFFLQNx4_AND2x2_ASAP7_75t_L?

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Figured it out on Dec. 27, 2019.

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setTieHiLoMode -cell “TIELOx1_ASAP7_75t_L TIEHIx1_ASAP7_75t_L” -maxDistance 5.1 -maxFanout 4
addTieHiLo -cell “TIELOx1_ASAP7_75t_L TIEHIx1_ASAP7_75t_L”
verifyTieCell > verifyTieCell_[clock format [clock second] -format %m%d%y_%H%M%S].log

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MAJx2_DFFLQNx4_OR2x2_ASAP7_75t_L reg2 ( .D1( n1 ), .D2( n15 ), .D3(1’b1), .Y( n2 ), .CLK( clk ) );
MAJx2_DFFLQNx4_AND2x2_ASAP7_75t_L reg4 ( .D1( n3 ), .D2( n5 ), .D3(1’b0), .Y( n16 ), .CLK( clk ) );
MAJx2_DFFLQNx4_OR2x2_ASAP7_75t_L reg5 ( .D1( n1 ), .D2( n6 ), .D3(1’b1), .Y( n4 ), .CLK( clk ) );
MAJx2_DFFLQNx4_OR2x2_ASAP7_75t_L reg7 ( .D1( n17 ), .D2( n7 ), .D3(1’b1), .Y( out2 ), .CLK( clk ) );

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clearGlobalNets
globalNetConnect VDD -type pgpin -pin VDD -inst * -module {}
globalNetConnect VSS -type pgpin -pin VSS -inst * -module {}
globalNetConnect VDD -type tiehi -pin VDD -inst * -module {}
globalNetConnect VSS -type tielo -pin VSS -inst * -module {}

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But the issue appears: place_design remove the BUF inserted.